1. Field of the Invention
This invention relates generally to a semiconductor memory device, and, more specifically, to providing an efficient capacitance switching for a tunable delay circuit.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly densely packed electrically conducting lines may also be formed in the semiconductor substrate. By forming selected electrical connections between selected semiconductor devices and selected conducting lines, circuits capable of performing complex functions may be created. For example, bits of data may be stored by providing electrical current to a plurality of bit lines and an orthogonal plurality of word lines that may be electrically coupled to one or more capacitors in a semiconductor memory.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets, of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity may be divided into 64 sub-arrays, each having 256K (218) memory cells.
Flash memory (sometimes called “flash RAM”) is a type of non-volatile memory that can be erased and reprogrammed in units of memory called blocks. Other types of memory may be erased and rewritten in smaller units, such as units at the byte level, which is more flexible, but slower than the block operations of flash memory. Flash memory is commonly used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written in block (rather than byte) sizes, making it faster to update. Applications employing flash memory include digital cellular phones, digital cameras, LAN switches, computers, digital set-up boxes, embedded controllers, and other devices.
Typically, digital systems, such as memory systems, may comprise a delay lock loop that may be used to align the edges of a plurality of digital signals. For example, a delay lock loop circuit may be used to align the rising edge and/or the falling edge of a clock signal based upon a reference clock signal, to produce a synchronized clock signal. Many times, digital signals from multiple sources access one or more memory spaces in a memory unit. It is desirable that these digital signals be synchronized for proper access of memory. Typical delay lock loops comprise a phase detect unit that detects the phase differences between a plurality of signals. The output of the phase detect unit is then used to affect the operation of a filter that adjusts the delay of an output of the delay lock loop.
The problems associated with the current methodologies of implementing the delay lock loop include an overreaction when performing delay compensation due to external factors on a digital line. Among the problems associated with current methodologies include utilizing multiplexers to control a number of capacitances, which are used to implement capacitive delays, to compensate for delay in the delay lock loop circuitry. However, the utilization of multiplexers to control the capacitors may cause various problems because of the inherent electrical characteristics of the capacitors and the resistance of the multiplexers. For example, multiplexers that are used to control the addition or elimination of capacitances (i.e., capacitive delays) to acquire the desired delay may be affected by its inherent resistivity. The resistance of the multiplexers may isolate capacitances from other components in a delay lock loop. Furthermore, the resistivity of the capacitance affects the RC time constant of the entire circuit in the delay lock loop, which may be affected by process, temperature or voltage variations. In other words, the time constant associated with the resistivity of the multiplexer and the capacitances used for the delay may be adversely affected by external factors, such as temperature, voltage or manufacturing processes. It would be desirable to implement a solution that may reduce the dependence on the aforementioned resistivity, thereby reducing the dependency on temperature, voltage or processes associated with a particular device.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.